A phase-locked loop (PLL), in one form, includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) a frequency divider, and a reference frequency signal source. The PLL synthesizes a frequency source signal, for example the VCO, based on the reference frequency signal source (reference signal), for example a crystal oscillator. The phase detector keeps the frequency source and reference signals at its input equal in frequency and phase by determining a phase mismatch between the divided frequency source and reference signals, and activating the charge pump based on the amount of phase mismatch. Because of device physics, loop dynamics and system architecture, the correction cannot be made instantaneously, resulting in a finite time between the detected phase mismatch between the reference and frequency source signals and the correction of the frequency source signal. The time for the frequency source signal to achieve its intended frequency (reference frequency) is called the "lock time" of the PLL.
A digital phase detector may consist of flip-flops clocked by the edges of derivatives of the reference and frequency source signals. If one edge arrives before the other, a charge is transferred to or from a loop filter that changes the frequency of the frequency source to align the edges. The amount of charge transferred (the amount of correction) depends on the time difference between the edges of the reference and frequency source signals. However, the operating range of the digital phase detector is only -2.pi. to 2.pi.. An edge of the reference signal must be received for each edge of the frequency source signal for proper correction to occur. If the difference between the reference and frequency source signals is too great, two edges may appear at an input before the corresponding edge arrives at the other input. Such a situation is called a cycle slip, and leads to an improper correction, causing increased PLL lock time.
One solution to overcome the cycle slip is to extend the range of the digital phase detector. When extending the range, edges of the reference and frequency source signals are each accounted for, and as long as one input of the detector has received more edges than the other input, a correction is enabled. However, a disadvantage of simply extending the range of the phase detector is the increased overshoot in the frequency source control voltage. In voltage-limited applications, the tuning sensitivity of the voltage-controlled oscillator must be increased, resulting in higher noise, or the control voltage will reach a limit where it clips. Should the control voltage clip, the improvements in PLL lock time from using the extended range digital phase detector would be lost or even reversed.
The present invention is directed to overcoming one or more of the problems discussed above in a novel and simple manner.